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Si4735-D60-GU2 参数 Datasheet PDF下载

Si4735-D60-GU2图片预览
型号: Si4735-D60-GU2
PDF下载: 下载PDF文件 查看货源
内容描述: 广播的AM / FM / SW / LW无线电接收器 [BROADCAST AM/FM/SW/LW RADIO RECEIVER]
分类和应用: 无线
文件页数/大小: 44 页 / 389 K
品牌: SILICON [ SILICON ]
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Si4730/31/34/35-D60  
4.8. Digital Audio Interface  
The digital audio interface operates in slave mode and  
supports a variety of MSB-first audio data formats  
including I2S and left-justified modes. The interface has  
three pins: digital data input (DIN), digital frame  
synchronization input (DFS), and  
a
digital bit  
synchronization input clock (DCLK). The Si473x-D60  
supports a number of industry-standard sampling rates  
including 32, 44.1, and 48 kHz. The digital audio  
interface enables low-power operation by eliminating  
the need for redundant DACs and ADCs on the audio  
baseband processor.  
4.8.1. Audio Data Formats  
The digital audio interface operates in slave mode and  
supports three different audio data formats:  
I2S  
Left-Justified  
DSP Mode  
In I2S mode, by default the MSB is captured on the  
second rising edge of DCLK following each DFS  
transition. The remaining bits of the word are sent in  
order, down to the LSB. The left channel is transferred  
first when the DFS is low, and the right channel is  
transferred when the DFS is high.  
In left-justified mode, by default the MSB is captured on  
the first rising edge of DCLK following each DFS  
transition. The remaining bits of the word are sent in  
order, down to the LSB. The left channel is transferred  
first when the DFS is high, and the right channel is  
transferred when the DFS is low.  
In DSP mode, the DFS becomes a pulse with a width of  
1DCLK period. The left channel is transferred first,  
followed right away by the right channel. There are two  
options in transferring the digital audio data in DSP  
mode: the MSB of the left channel can be transferred on  
the first rising edge of DCLK following the DFS pulse or  
on the second rising edge.  
In all audio formats, depending on the word size, DCLK  
frequency, and sample rates, there may be unused  
DCLK cycles after the LSB of each word before the next  
DFS transition and MSB of the next word. In addition, if  
preferred, the user can configure the MSB to be  
captured on the falling edge of DCLK via properties.  
The number of audio bits can be configured for 8, 16,  
20, or 24 bits.  
4.8.2. Audio Sample Rates  
The device supports a number of industry-standard  
sampling rates including 32, 44.1, and 48 kHz. The  
digital audio interface enables low-power operation by  
eliminating the need for redundant DACs on the audio  
baseband processor.  
Rev. 1.1  
25  
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