Si3056
Si3018/19/10
The capacitive communications link is disabled by
default. To enable it, the PDL bit (Register 6, bit 4) must
be cleared. No communication between the system-
side and line-side can occur until this bit is cleared. The
clock generator must be programmed to an acceptable
sample rate before clearing the PDL bit.
5.3. Power Supplies
The Si3056 system-side device operates from a 3.0–
3.6 V power supply. The Si3056 input pins are 5 V
tolerant. The Si3056 output pins only drive 3.3 V. The
line-side device derives its power from two sources: The
Si3056 and the telephone line. The Si3056 supplies
power over the patented isolation link between the two
devices, allowing the line-side device to communicate
with the Si3056 while on-hook and perform other on-
hook functions such as line voltage monitoring. When
off-hook, the line-side device also derives power from
the line current supplied from the telephone line. This
5.6. Transmit/Receive Full Scale Level
(Si3019 Line-Side Only)
The Si3056 supports programmable maximum transmit
and receive levels. The default signal level supported by
the Si3056 is 0 dBm into a 600 Ω load. Two additional
modes of operation offer increased transmit and receive
level capability to enable use of the DAA in applications
that require higher signal levels. The full scale mode is
enabled by setting the FULL bit in Register 31. With
FULL = 1, the full scale signal level increases to
+3.2 dBm into a 600 Ω load, or 1 dBV into all reference
impedances. The enhanced full scale mode (or 2X full
scale) is enabled by setting the FULL2 bit in Register
30. Will FULL2 = 1, the full scale signal level increases
to +6.0 dBm into a 600 Ω load, or 1.5 dBV into all
reference impedances. The full scale and enhanced full
scale modes provide the ability to trade off TX power
and TX distortion for a peak signal. By using the
programmable digital gain registers in conjunction with
the enhanced full scale signal level mode, a specific
power level (+3.2 dBm for example) could be achieved
across all ACT settings.
®
feature is exclusive to DAAs from Silicon Laboratories
and allows the most cost-effective implementation for a
DAA while still maintaining robust performance over all
line conditions.
5.4. Initialization
When the Si3056 is powered up, assert the RESET pin.
When the RESET pin is deasserted, the registers have
default values. This reset condition guarantees the line-
side device is powered down without the possibility of
loading the line (i.e., off-hook). An example initialization
procedure is outlined in the following list:
1. Program the PLL with registers 8 and 9 (N[7:0],
M[7:0]) to the appropriate divider ratios for the
supplied MCLK frequency and the sample rate in
register 7 (SRC), as defined in "5.25.Clock
Generation" on page 36.
5.7. Parallel Handset Detection
2. Wait 1 ms until the PLL is locked.
The Si3056 can detect a parallel handset going off-
hook. When the Si3056 is off-hook, the loop current can
be monitored with the LCS bits. A significant drop in
loop current signals that a parallel handset is going off-
hook. If a parallel handset causes the LCS bits to read
all 0s, the Drop-Out Detect (DOD) bit can be checked to
verify a valid line exists.
3. Write a 00H into Register 6 to power up the line-side
device.
4. Set the required line interface parameters (i.e.,
DCV[1:0], MINI[1:0], ILIM, DCR, ACT and ACT2 or
ACIM[3:0], OHS, RT, RZ, ATX[2:0] or TGA2 and
TXG2) as defined by “Country Specific Register
Settings” shown in Table 15.
The LVS bits can be read to determine the line voltage
when on-hook and off-hook. Significant drops in line
voltage can signal a parallel handset. For the Si3056 to
operate in parallel with another handset, the parallel
handset must have a sufficiently high dc termination to
support two off-hook DAAs on the same line. Improved
parallel handset operation can be achieved by changing
the dc impedance from 50 to 800 Ω and reducing the
DCT pin voltage with the DVC[1:0] bits.
When this procedure is complete, the Si3056 is ready
for ring detection and off-hook.
5.5. Isolation Barrier
The Si3056 achieves an isolation barrier through low-
cost, high-voltage capacitors in conjunction with Silicon
®
Laboratories proprietary signal processing techniques.
These techniques eliminate signal degradation from
capacitor mismatches, common mode interference, or
noise coupling. As shown in Figure 17 on page 18, the
C1, C2, C8, and C9 capacitors isolate the Si3056
(system-side) from the line-side device. Transmit,
receive, control, ring detect, and caller ID data are
passed across this barrier. Y2 class capacitors can be
used to achieve surge performance of 5 kV or greater.
5.8. Line Voltage/Loop Current Sensing
The Si3056 can measure loop current and line voltage
with the Si3010, Si3018, and the Si3019 line-side
devices. The 8-bit LCS2[7:0] and LCS[4:0] registers
report loop current. The 8-bit LVS[7:0] register reports
line voltage.
Rev. 1.05
25
SILICON [ SILICON ]
