Si1000/1/2/3/4/5
17. Voltage Regulator (VREG0)
Si1000/1/2/3/4/5 devices include an internal voltage regulator (VREG0) to regulate the internal core supply
to 1.8 V from a VDD_MCU supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are
specified in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, saving approximately 80 µA in
all non-Sleep power modes. This bias should only be disabled when the precision oscillator is not being
used.
The internal regulator (VREG0) is disabled when the device enters Sleep Mode and remains enabled
when the device enters Suspend Mode. See Section “14. Power Management” on page 151 for complete
details about low power modes.
SFR Definition 17.1. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
Reserved Reserved OSCBIAS
Reserved
Name
Type
Reset
R
0
R/W
0
R/W
0
R/W
1
R
0
R
0
R
0
R/W
0
SFR Page = 0x0; SFR Address = 0xC9
Bit
Name
Function
7
Unused Read = 0b. Write = Don’t care.
Reserved Read = 0b. Must Write 0b.
OSCBIAS Precision Oscillator Bias.
6:5
4
When set to 1, the bias used by the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to save approximately 80 µA
of supply current in all non-Sleep power modes. If disabled then re-enabled, the pre-
cision oscillator bias requires 4 µs of settling time.
3:1
0
Unused Read = 000b. Write = Don’t care.
Reserved Read = 0b. Must Write 0b.
17.1. Voltage Regulator Electrical Specifications
See Table 4.15 on page 65 for detailed Voltage Regulator Electrical Specifications.
174
Rev. 1.0
SILICON [ SILICON ]
