Si1000/1/2/3/4/5
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration
Bit
7
6
5
4
3
2
ILIMIT
R/W
0
1
0
Name Reserved
CLKDIV[1:0]
AD0CKINV CLKINV
VDDSLP CLKSEL
Type
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Page = 0x0; SFR Address = 0x96
Bit
Name
Function
7
Reserved Read = 0b; Must write 0b.
6:5 CLKDIV[1:0]
DC-DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4
AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3
2
CLKINV
DC-DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
ILIMIT
Peak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current. See Table 16.1
for peak inductor current levels.
0: Peak inductor current is set at a lower level.
1: Peak inductor current is set at a higher level.
1
0
VDDSLP
VDD_MCU/DC+ Sleep Mode Connection.
Specifies the power source for VDD_MCU/DC+ in Sleep Mode when the dc-dc con-
verter is enabled.
0: VDD_MCU/DC+ connected to VBAT in Sleep Mode.
1: VDD_MCU/DC+ is floating in Sleep Mode.
CLKSEL
DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
172
Rev. 1.0
SILICON [ SILICON ]
