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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
SFR Definition 26.8. SPI0CN: SPI0 Control  
Bit  
7
SPIF  
R/W  
0
6
WCOL  
R/W  
0
5
MODF  
R/W  
0
4
RXOVRN  
R/W  
3
2
1
0
SPIEN  
R/W  
0
Name  
Type  
Reset  
NSSMD[1:0]  
R/W  
TXBMT  
R
1
0
0
1
SFR Page = 0x0; SFR Address = 0xF8; Bit-Addressable  
Bit  
Name  
Function  
7
SPIF  
SPI0 Interrupt Flag.  
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts  
are enabled, an interrupt will be generated. This bit is not automatically cleared by  
hardware, and must be cleared by software.  
6
5
4
WCOL  
MODF  
Write Collision Flag.  
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When  
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be  
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not  
automatically cleared by hardware, and must be cleared by software.  
Mode Fault Flag.  
This bit is set to logic 1 by hardware when a master mode collision is detected  
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an  
interrupt will be generated. This bit is not automatically cleared by hardware, and  
must be cleared by software.  
RXOVRN  
Receive Overrun Flag (valid in slave mode only).  
This bit is set to logic 1 by hardware when the receive buffer still holds unread data  
from a previous transfer and the last bit of the current transfer is shifted into the  
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This  
bit is not automatically cleared by hardware, and must be cleared by software.  
3:2 NSSMD[1:0] Slave Select Mode.  
Selects between the following NSS operation modes:  
(See Section 26.2 and Section 26.3).  
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.  
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.  
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the  
device and will assume the value of NSSMD0.  
1
0
TXBMT  
SPIEN  
Transmit Buffer Empty.  
This bit will be set to logic 0 when new data has been written to the transmit buffer.  
When data in the transmit buffer is transferred to the SPI shift register, this bit will  
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.  
SPI0 Enable.  
0: SPI disabled.  
1: SPI enabled.  
Rev. 1.0  
325