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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
SFR Definition 26.7. SPI0CFG: SPI0 Configuration  
Bit  
7
6
MSTEN  
R/W  
0
5
CKPHA  
R/W  
0
4
CKPOL  
R/W  
0
3
2
1
SRMT  
R
0
Name SPIBSY  
SLVSEL  
NSSIN  
RXBMT  
Type  
R
0
R
0
R
1
R
1
Reset  
1
SFR Page = 0x0; SFR Address = 0xA1  
Bit  
Name  
Function  
7
SPIBSY  
SPI Busy.  
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).  
6
5
4
3
MSTEN  
CKPHA  
CKPOL  
SLVSEL  
Master Mode Enable.  
0: Disable master mode. Operate in slave mode.  
1: Enable master mode. Operate as a master.  
SPI0 Clock Phase.  
*
0: Data centered on first edge of SCK period.  
1: Data centered on second edge of SCK period.  
*
SPI0 Clock Polarity.  
0: SCK line low in idle state.  
1: SCK line high in idle state.  
Slave Selected Flag.  
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected  
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does  
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-  
sion of the pin input.  
2
1
NSSIN  
SRMT  
NSS Instantaneous Pin Input.  
This bit mimics the instantaneous value that is present on the NSS port pin at the  
time that the register is read. This input is not de-glitched.  
Shift Register Empty (valid in slave mode only).  
This bit will be set to logic 1 when all data has been transferred in/out of the shift  
register, and there is no new information available to read from the transmit buffer  
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to  
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when  
in Master Mode.  
0
RXBMT  
Receive Buffer Empty (valid in slave mode only).  
This bit will be set to logic 1 when the receive buffer has been read and contains no  
new information. If there is new information available in the receive buffer that has  
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.  
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is  
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.  
See Table 26.1 for timing parameters.  
324  
Rev. 1.0