Si1000/1/2/3/4/5
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/
Description
08 R/W Operating &
Function
antdiv[2] antdiv[1] antdiv[0]
rxmpk
autotx
enldm
ffclrrx
ffclrtx
00h
Control 2
7C R/W
7D R/W
TX FIFO
Control 1
Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h
TX FIFO
Control 2
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When
the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcon-
troller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/
Description
7E R/W
RX FIFO
Control
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be
enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and “Register 06h. Inter-
rupt Enable 2.” If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin
but the bits will still be read correctly in the Interrupt Status registers.
23.6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Reg-
ister 30h. Data Access Control" through “Register 4Bh. Received Packet Length” control the configuration,
status, and decoded RX packet data for Packet Handling. The usual fields for network communication
(such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be auto-
matically added to the data payload. The fields needed for packet generation normally change infrequently
and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the transceiver.
The general packet structure is shown in Figure 23.12. The length of each field is shown below the field.
The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields
have programmable lengths to accommodate different applications. The most common CRC polynominals
are available for selection.
Data
CRC
Preamble
1-255 Bytes
1-4 Bytes
0 or 2
Bytes
Figure 23.12. Packet Structure
An overview of the packet handler configuration registers is shown in Table 23.4.
262
Rev. 1.0
SILICON [ SILICON ]
