Si1000/1/2/3/4/5
enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All
enabled interrupt bits will be cleared when the corresponding interrupt status register is read. If the inter-
rupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at
anytime in the Interrupt Status registers.
Important Note: The nIRQ line should not be monitored for POR after SDN or initial power up. The POR
signal is available by default on GPIO0 and GPIO1 and should be monitored as an alternative to nIRQ for
POR. As an alternative, software may wait 18 ms after SDN rising before polling the interrupt status regis-
ters in 03h and 04h to check for POR and chip ready (XTAL start-up/ready). This process may take up to
26 ms. After the initial interrupt is cleared, the operation of the nIRQ pin will be normal.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
03
04
R
R
Interrupt Status 1
ifferr
itxffafull
itxffaem
irxffafull
irssi
iext ipksent ipkvalid icrcerror
iwut ilbd ichiprdy ipor
—
—
Interrupt Status 2 iswdet ipreaval ipreainval
05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
06 R/W Interrupt Enable 2 enswdet enpreava enpreainval enrssi enwut enlbd enchiprdy enpor
00h
01h
See “AN440: EZRadioPRO Detailed Register Descriptions” for a complete list of interrupts.
23.3. System Timing
The system timing for TX and RX modes is shown in Figures 23.2 and 23.3. The figures demonstrate tran-
sitioning from STANDBY mode to TX or RX mode through the built-in sequencer of required steps. The
user only needs to program the desired mode, and the internal sequencer will properly transition the part
from its current mode.
The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow
for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting
of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain
applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact appli-
cations support if faster turnaround time is desired.
XTAL Settling
TX Packet
Time
600us
Figure 23.2. TX Timing
244
Rev. 1.0
SILICON [ SILICON ]
