Si1000/1/2/3/4/5
21. Port Input/Output
Digital and analog resources are available through 19 or 16 I/O pins. The EZRadioPRO peripheral pro-
vides an additional 3 GPIO pins which are independent of the pins described in this chapter. Port pins are
organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O
pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Ana-
log I/O pins are used by the internal analog resources. P1.0, P1.1, P1.2, and P1.4 are dedicated for com-
munication with the EZRadioPRO peripheral. P1.3 is not available. P2.4, P2.5, and P2.6 are only available
on the Si1000/1/2/3. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D).
See Section “29. C2 Interface” on page 371 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Px.x Port I/Os are 5V tolerant when used as digital inputs or open-drain outputs. For Port I/Os config-
ured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog func-
tions can operate up to the VDD_MCU supply voltage. See Section 21.1 for more information on Port I/O
operating modes and the electrical specifications chapter for detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
External Interrupts
EX0 and EX1
Priority
Decoder
PnMDOUT,
PnMDIN Registers
2
UART
Highest
Priority
4
2
SPI0
SPI1
P0.0
P0.7
SMBus
P0
I/O
Cells
Digital
Crossbar
8
8
CP0
CP1
Outputs
4
P1.5
P1.6
P1.7
SYSCLK
PCA
P1
I/O
Cells
7
2
Lowest
Priority
T0, T1
8
P2.0
8
P0
P1
P2
(P0.0-P0.7)
P2
I/O
Cell
P2.6
P2.7
8
(P1.0-P1.7)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
No analog functionality
available on P2.7
8
(P2.0-P2.7)
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the
EZRadioPRO peripheral. P1.3 is not internally or externally connected.
P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3
Figure 21.1. Port I/O Functional Block Diagram
Rev. 1.0
207
SILICON [ SILICON ]
