Si1000/1/2/3/4/5
Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control
Bit
7
6
5
4
3
2
1
0
AGCEN
XMODE
BIASX2
CLKVLD
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
SmaRTClock Address = 0x05
Bit
Name
Function
7
AGCEN SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
0: AGC disabled.
1: AGC enabled.
6
5
XMODE SmaRTClock Oscillator Mode.
Selects Crystal or Self Oscillate Mode.
0: Self-Oscillate Mode selected.
1: Crystal Mode selected.
BIASX2 SmaRTClock Oscillator Bias Double Enable.
Enables/disables the Bias Double feature.
0: Bias Double disabled.
1: Bias Double enabled.
4
CLKVLD SmaRTClock Oscillator Crystal Valid Indicator.
Indicates if oscillation amplitude is sufficient for maintaining oscillation.
0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation.
1: Sufficient oscillation amplitude detected.
3:0
Unused Read = 0000b; Write = Don’t Care.
204
Rev. 1.0
SILICON [ SILICON ]
