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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
ground reference of the external analog input signal. When using the ADC with the dc-dc converter, we  
also recommend enabling the SYNC bit in the DC0CN register to minimize interference.  
These general guidelines provide the best performance in most applications, though some situations may  
benefit from experimentation to eliminate any residual noise issues. Examples might include tying the  
grounds together, using additional low-inductance decoupling caps in parallel with the recommended ones,  
investigating the effects of different dc-dc converter settings, etc.  
16.6. Selecting the Optimum Switch Size  
The dc-dc converter has two built-in switches (the diode bypass switch and duty cycle control switch). To  
maximize efficiency, one of two switch sizes may be selected. The large switches are ideal for carrying  
high currents and the small switches are ideal for low current applications. The ideal switchover point to  
switch from the small switches to the large switches varies with the programmed output voltage. At an out-  
put voltage of 2 V, the ideal switchover point is at approximately 4 mA total output current. At an output  
voltage of 3 V, the ideal switchover point is at approximately 8 mA total output current.  
16.7. DC-DC Converter Clocking Options  
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, select-  
able by the CLKSEL bit (DC0CF.0). The dc-dc converter internal oscillator frequency is approximately  
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of the system clock may  
be used as the dc-dc clock source. The dc-dc converter has a built in clock divider (configured using  
DC0CF[6:5]) which allows any system clock frequency over 1.6 MHz to generate a valid clock in the range  
of 1.6 to 3.2 MHz.  
When the precision internal oscillator is selected as the system clock source, the OSCICL register may be  
used to fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should  
only be decreased since it is factory calibrated at its maximum frequency. The minimum frequency which  
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The  
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit  
(DC0CF.3) to logic 1. These options can be used to minimize interference in noise sensitive applications.  
16.8. DC-DC Converter Behavior in Sleep Mode  
When the Si1000/1/2/3/4/5 devices are placed in Sleep mode, the dc-dc converter is disabled, and the  
VDD_MCU/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO  
pins are powered from a low-impedance source during sleep mode. If the GPIO pins are not used as  
inputs or outputs during sleep mode, then the VDD_MCU/DC+ output can be made to float during Sleep  
mode by setting the VDDSLP bit in the DC0CF register to 1.  
Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the  
VDD_MCU/DC+ load current (include leakage currents) is negligible, then the capacitor on  
VDD_MCU/DC+ will maintain the output voltage near the programmed value, which means that the  
VDD_MCU/DC+ capacitor will not need to be recharged upon every wake up event. The second power  
advantage is that internal or external low-power circuits that require more than 1.8 V can continue to func-  
tion during Sleep mode without operating the dc-dc converter, powered by the energy stored in the 1 µF  
output decoupling capacitor. For example, the Si1004/5 comparators require about 0.4 µA when operating  
in their lowest power mode. If the dc-dc converter output were increased to 3.3 V just before putting the  
device into Sleep mode, then the comparator could be powered for more than 3 seconds before the output  
voltage dropped to 1.8 V. In this example, the overall energy consumption would be much lower than if the  
dc-dc converter were kept running to power the comparator.  
If the load current on VDD_MCU/DC+ is high enough to discharge the VDD_MCU/DC+ capacitance to a  
voltage lower than VBAT during the sleep interval, an internal diode will prevent VDD_MCU/DC+ from  
dropping more than a few hundred millivolts below VBAT. There may be some additional leakage current  
Rev. 1.0  
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