Si1000/1/2/3/4/5
13.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the Flash
byte at address 0xFFFE.
The value of the Flash byte at address 0xFFFE can be decoded as follows:
0xD0—Si1000
0xD1—Si1001
0xD2—Si1002
0xD3—Si1003
13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F92x-C8051F93x devices for the Flash to be successfully modified. If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum V rise time specification of 1 ms is met. If the system cannot meet
DD
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until V reaches the minimum device operating voltage and re-asserts RST if
DD
V
drops below the minimum device operating voltage.
DD
3. Keep the on-chip VDD Monitor enabled and enable the V Monitor as a reset source as early in code
DD
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
Monitor and enabling the V Monitor as a reset source. Code examples showing this can be
DD
DD
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
Notes: On Si1000/1/2/3/4/5 devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase Flash without generating a Flash Error Device Reset.
On Si1000/1/2/3/4/5 devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the V Monitor and enable the V Monitor as a reset
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DD
source inside the functions that write and erase Flash memory. The V Monitor enable instructions
DD
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
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SILICON [ SILICON ]
