Si1000/1/2/3/4/5
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
AD0SC[4:0]
AD08BE
AD0TM
AMP0GN
Name
Type
Reset
R/W
1
R/W
0
R/W
0
R/W
0
1
1
1
1
SFR Page = 0x0; SFR Address = 0xBC
Bit Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.9.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
FCLK
AD0SC = ------------------- – 1 *
CLKSAR
*Round the result up.
or
FCLK
CLKSAR = ----------------------------
AD0SC + 1
2
1
AD08BE
AD0TM
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately fol-
lowing the start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock
cycles following the start-of-conversion signal. The ADC is allowed to track during
this time.
0
AMP0GN ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
82
Rev. 1.0
SILICON [ SILICON ]
