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SI1005-C-GM 参数 Datasheet PDF下载

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型号: SI1005-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
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文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has  
a total of 109 instructions. The table below shows the total number of instructions that require each execu-  
tion time.  
Clocks to Execute  
1
2
2/3  
5
3
3/4  
7
4
3
4/5  
1
5
2
8
1
Number of Instructions  
26  
50  
14  
8.2. Programming and Debugging Support  
In-system programming of the Flash program memory and communication with on-chip debug support  
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).  
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware  
breakpoints, starting, stopping and single stepping through program execution (including interrupt service  
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-  
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or  
other on-chip resources. C2 details can be found in Section “29. C2 Interface” on page 371.  
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-  
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's  
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-  
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-  
able.  
8.3. Instruction Set  
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-  
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51  
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,  
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-  
dard 8051.  
8.3.1. Instruction and CPU Timing  
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with  
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based  
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.  
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock  
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock  
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the  
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock  
cycles for each instruction.  
110  
Rev. 1.0