EFR32MG13 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
12: PC10 16: PD11 20: PD15 24: PF3
Functionality
0 - 3
0: PA3
1: PA4
2: PA5
3: PB11
0: PA4
1: PA5
2: PB11
3: PB12
0: PA5
1: PB11
2: PB12
3: PB13
0: PA1
1: PA2
2: PA3
3: PA4
4 - 7
4: PB12
5: PB13
6: PB14
7: PB15
4: PB13
5: PB14
6: PB15
7: PC6
8 - 11
8: PC6
9: PC7
10: PC8
11: PC9
8: PC7
9: PC8
10: PC9
11: PC10
8: PC8
9: PC9
20 - 23
24 - 27
28 - 31
28: PF7
29: PA0
30: PA1
31: PA2
28: PA0
29: PA1
30: PA2
31: PA3
28: PA1
29: PA2
30: PA3
31: PA4
28: PF5
29: PF6
30: PF7
31: PA0
Description
13: PC11 17: PD12 21: PF0
15: PD10 18: PD13 22: PF1
19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
24: PF4
25: PF5
26: PF6
27: PF7
24: PF5
25: PF6
26: PF7
27: PA0
USART1 chip se-
lect input / output.
US1_CS
12: PC11 16: PD12 20: PF0
14: PD10 17: PD13 21: PF1
15: PD11 18: PD14 22: PF2
19: PD15 23: PF3
USART1 Clear To
Send hardware
flow control input.
US1_CTS
US1_RTS
4: PB14
5: PB15
6: PC6
13: PD10 16: PD13 20: PF1
14: PD11 17: PD14 21: PF2
USART1 Request
To Send hardware
flow control output.
10: PC10 15: PD12 18: PD15 22: PF3
7: PC7
11: PC11
8: PB14
9: PB15
10: PC6
11: PC7
19: PF0
23: PF4
4: PA5
12: PC8
13: PC9
17: PD10 20: PD13 24: PF1
18: PD11 21: PD14 25: PF2
USART1 Asynchro-
nous Receive.
5: PB11
6: PB12
7: PB13
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_RX
14: PC10 19: PD12 22: PD15 26: PF3
15: PC11
23: PF0
27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
18: PD10 21: PD13 25: PF1
19: PD11 22: PD14 26: PF2
23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
10: PB15 14: PC9
US1_TX
11: PC6
15: PC10
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
12: PF0
13: PF1
14: PF3
15: PF4
12: PF1
13: PF3
14: PF4
15: PF5
12: PF3
13: PF4
14: PF5
15: PF6
16: PF5
17: PF6
18: PF7
30: PA5
29: PA5
28: PA5
USART2 clock in-
put / output.
US2_CLK
US2_CS
11: PF0
16: PF6
17: PF7
USART2 chip se-
lect input / output.
10: PF0
11: PF1
16: PF7
USART2 Clear To
Send hardware
flow control input.
US2_CTS
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