EFM32G Data Sheet
System Overview
3.2.9 EFM32G842
The features of the EFM32G842 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.9. EFM32G842 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
NA
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
Full configuration
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
US2_TX, US2_RX, US2_CLK, US2_CS
LEU0_TX, LEU0_RX
LEU1_TX, LEU1_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
USART0
USART1
USART2
LEUART0
LEUART1
TIMER0
TIMER1
TIMER2
RTC
Full configuration with IrDA
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with DTI
Full configuration
Full configuration
TIM2_CC[2:0]
Full configuration
NA
LETIMER0
PCNT0
PCNT1
PCNT2
ACMP0
ACMP1
VCMP
ADC0
Full configuration
LET0_O[1:0]
Full configuration, 8-bit count register
Full configuration, 8-bit count register
Full configuration, 8-bit count register
Full configuration
PCNT0_S[1:0]
PCNT1_S[1:0]
PCNT2_S[1:0]
ACMP0_CH[3:0], ACMP0_O
ACMP1_CH[7:4], ACMP1_O
NA
Full configuration
Full configuration
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[0]
AES
Full configuration
NA
GPIO
53 pins
Available pins are shown in Table 4.3 (p. 57)
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