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EFM32G200F16G-E-QFN32R 参数 Datasheet PDF下载

EFM32G200F16G-E-QFN32R图片预览
型号: EFM32G200F16G-E-QFN32R
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller,]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 205 页 / 3175 K
品牌: SILICON [ SILICON ]
 浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第134页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第135页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第136页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第137页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第139页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第140页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第141页浏览型号EFM32G200F16G-E-QFN32R的Datasheet PDF文件第142页  
EFM32G Data Sheet  
Pin Definitions  
Alternate  
LOCATION  
Functionality  
TIM0_CC0  
TIM0_CC1  
TIM0_CC2  
TIM0_CDTI0  
TIM0_CDTI1  
TIM0_CDTI2  
TIM1_CC0  
TIM1_CC1  
TIM1_CC2  
TIM2_CC0  
TIM2_CC1  
TIM2_CC2  
US0_CLK  
0
1
2
3
Description  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA0  
PA1  
PA2  
PD1  
PD2  
PD3  
Timer 0 Capture Compare input / output channel 0.  
Timer 0 Capture Compare input / output channel 1.  
Timer 0 Capture Compare input / output channel 2.  
Timer 0 Complimentary Deat Time Insertion channel 0.  
Timer 0 Complimentary Deat Time Insertion channel 1.  
Timer 0 Complimentary Deat Time Insertion channel 2.  
Timer 1 Capture Compare input / output channel 0.  
Timer 1 Capture Compare input / output channel 1.  
Timer 1 Capture Compare input / output channel 2.  
Timer 2 Capture Compare input / output channel 0.  
Timer 2 Capture Compare input / output channel 1.  
Timer 2 Capture Compare input / output channel 2.  
USART0 clock input / output.  
PC13  
PC14  
PC15  
PE10  
PE11  
PE12  
PA12  
PA13  
PA14  
PE5  
PF3  
PF4  
PF5  
PC13  
PC14  
PC15  
PC13  
PC14  
PC15  
PE12  
PE13  
US0_CS  
PE4  
USART0 chip select input / output.  
USART0 Asynchronous Receive.  
US0_RX  
US0_TX  
PE11  
PE10  
PE6  
PE7  
USART0 Synchronous mode Master Input / Slave Output (MI-  
SO).  
USART0 Asynchronous Transmit.Also used as receive input  
in half duplex communication.  
USART0 Synchronous mode Master Output / Slave Input  
(MOSI).  
US1_CLK  
US1_CS  
PB7  
PB8  
PD2  
PD3  
USART1 clock input / output.  
USART1 chip select input / output.  
USART1 Asynchronous Receive.  
US1_RX  
US1_TX  
PD1  
PD0  
USART1 Synchronous mode Master Input / Slave Output (MI-  
SO).  
USART1 Asynchronous Transmit.Also used as receive input  
in half duplex communication.  
USART1 Synchronous mode Master Output / Slave Input  
(MOSI).  
US2_CLK  
US2_CS  
PC4  
PC5  
PB5  
PB6  
USART2 clock input / output.  
USART2 chip select input / output.  
USART2 Asynchronous Receive.  
US2_RX  
US2_TX  
PB4  
PB3  
USART2 Synchronous mode Master Input / Slave Output (MI-  
SO).  
USART2 Asynchronous Transmit.Also used as receive input  
in half duplex communication.  
USART2 Synchronous mode Master Output / Slave Input  
(MOSI).  
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