C8051F52x-53x
List of Figures
1. System Overview
Figure 1.1. C8051F530 Block Diagram.................................................................... 19
Figure 1.2. C8051F520 Block Diagram.................................................................... 20
Figure 1.3. Development/In-System Debug Diagram............................................... 22
Figure 1.4. Memory Map .......................................................................................... 23
Figure 1.5. 12-Bit ADC Block Diagram..................................................................... 25
Figure 1.6. Comparator Block Diagram.................................................................... 26
Figure 1.7. Port I/O Functional Block Diagram......................................................... 27
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. TSSOP-20 Package Diagram ................................................................ 37
Figure 4.2. QFN-20 Package Diagram..................................................................... 38
Figure 4.3. QFN-10 Package Diagram..................................................................... 39
5. 12-Bit ADC (ADC0)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 41
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 42
Figure 5.3. ADC0 Tracking Modes........................................................................... 44
Figure 5.4. 12-Bit ADC Tracking Mode Example ..................................................... 45
Figure 5.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4............... 46
Figure 5.6. ADC0 Equivalent Input Circuits.............................................................. 48
Figure 5.7. ADC Window Compare Example: Right-Justified Single-Ended Data... 56
Figure 5.8. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 56
6. Voltage Reference
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 63
7. Voltage Regulator (REG0)
Figure 7.1. External Capacitors for Voltage Regulator Input/Output........................ 67
8. Comparator
Figure 8.1. Comparator Functional Block Diagram .................................................. 69
Figure 8.2. Comparator Hysteresis Plot ................................................................... 70
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram............................................................................ 75
10.Memory Organization and SFRs
Figure 10.1. Memory Map ........................................................................................ 85
11.Interrupt Handler
12.Reset Sources
Figure 12.1. Reset Sources...................................................................................... 99
Figure 12.2. Power-On and V Monitor Reset Timing ......................................... 100
DD
13.Flash Memory
Figure 13.1. Flash Program Memory Map.............................................................. 112
14.Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram..................................................... 117
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 118
Rev. 0.3
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SILICON [ SILICON ]
