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C8051F530-IM 参数 Datasheet PDF下载

C8051F530-IM图片预览
型号: C8051F530-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4/2 KB ISP功能的Flash MCU系列 [8/4/2 kB ISP Flash MCU Family]
分类和应用:
文件页数/大小: 220 页 / 2701 K
品牌: SILICON [ SILICON ]
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C8051F52x-53x  
15.1.1.Internal Oscillator Suspend Mode.......................................................... 134  
15.2.External Oscillator Drive Circuit...................................................................... 137  
15.2.1.Clocking Timers Directly Through the External Oscillator...................... 137  
15.2.2.External Crystal Example....................................................................... 137  
15.2.3.External RC Example............................................................................. 139  
15.2.4.External Capacitor Example................................................................... 139  
15.3.System Clock Selection.................................................................................. 141  
16.UART0.................................................................................................................... 143  
16.1.Enhanced Baud Rate Generation................................................................... 144  
16.2.Operational Modes ......................................................................................... 145  
16.2.1.8-Bit UART............................................................................................. 145  
16.2.2.9-Bit UART............................................................................................. 146  
16.3.Multiprocessor Communications .................................................................... 146  
17.LIN (C8051F520/523/526/530/533/536 only) ........................................................ 151  
17.1.Major Characteristics...................................................................................... 151  
17.2. Software Interface with the LIN Peripheral .................................................. 152  
17.3.LIN Registers.................................................................................................. 153  
17.3.1.LIN Direct Access SFR Registers Definition .......................................... 153  
17.3.2.LIN Indirect Access SFR Registers Definition........................................ 154  
17.4.LIN Interface Setup and Operation................................................................. 161  
17.4.1.Mode Definition ...................................................................................... 161  
17.4.2.Bit Rate Options: Manual or Autobaud (Slave only)............................... 162  
17.4.3.Baud Rate Calculations - Manual Mode................................................. 162  
17.4.4.Baud Rate Calculations - Automatic Mode ............................................ 164  
17.4.5.LIN Master Mode Operation................................................................... 165  
17.4.6.LIN Slave Mode Operation..................................................................... 166  
17.4.7.Sleep Mode and Wake-Up..................................................................... 167  
17.4.8.Error Detection and Handling................................................................. 168  
17.4.9.LIN Master Mode Operation................................................................... 168  
17.4.10.LIN Slave Mode Operation................................................................... 168  
18.Enhanced Serial Peripheral Interface (SPI0)...................................................... 171  
18.1.Signal Descriptions......................................................................................... 172  
18.1.1.Master Out, Slave In (MOSI).................................................................. 172  
18.1.2.Master In, Slave Out (MISO).................................................................. 172  
18.1.3.Serial Clock (SCK) ................................................................................. 172  
18.1.4.Slave Select (NSS) ................................................................................ 172  
18.2.SPI0 Master Mode Operation......................................................................... 173  
18.3.SPI0 Slave Mode Operation........................................................................... 174  
18.4.SPI0 Interrupt Sources ................................................................................... 175  
18.5.Serial Clock Timing......................................................................................... 175  
18.6.SPI Special Function Registers...................................................................... 176  
19.Timers.................................................................................................................... 185  
19.1.Timer 0 and Timer 1 ....................................................................................... 185  
Rev. 0.3  
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