欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F502-IM的Datasheet PDF文件第71页浏览型号C8051F502-IM的Datasheet PDF文件第72页浏览型号C8051F502-IM的Datasheet PDF文件第73页浏览型号C8051F502-IM的Datasheet PDF文件第74页浏览型号C8051F502-IM的Datasheet PDF文件第76页浏览型号C8051F502-IM的Datasheet PDF文件第77页浏览型号C8051F502-IM的Datasheet PDF文件第78页浏览型号C8051F502-IM的Datasheet PDF文件第79页  
C8051F50x-F51x  
9. Comparators  
The C8051F50x-F51x devices include two on-chip programmable voltage Comparators. A block diagram  
of the comparators is shown in Figure 9.1, where “n” is the comparator number (0 or 1). The two Compara-  
tors operate identically except that Comparator0 can also be used a reset source. For input selection  
details, refer to SFR Definition 9.5 and SFR Definition 9.6.  
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two  
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an  
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system  
clock is not active. This allows the Comparators to operate and generate an output with the device in  
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or  
push-pull (see Section “20.4. Port I/O Initialization” on page 182). Comparator0 may also be used as a  
reset source (see Section “17.5. Comparator0 Reset” on page 145).  
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 9.5). The CMX0P1-CMX0P0  
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative  
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 9.6). The CMX1P1-  
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1  
negative input.  
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-  
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the  
Crossbar (for details on Port configuration, see Section “20.1. Port I/O Modes of Operation” on page 178).  
CPTnCN  
VIO  
CPn +  
+
CPn  
Comparator  
Input Mux  
SET  
CLR  
SET  
CLR  
D
Q
Q
D
Q
Q
CPn -  
-
Crossbar  
(SYNCHRONIZER)  
CPnA  
GND  
Reset  
Decision  
Tree  
CPTnMD  
0
1
CPn  
Interrupt  
CPnEN  
EA  
CPnRIF  
CPnFIF  
0
0
1
1
0
1
Figure 9.1. Comparator Functional Block Diagram  
Rev. 1.1  
75  
 复制成功!