C8051F50x-F51x
SFR Definition 8.1. REF0CN: Reference Control
Bit
7
6
5
4
3
2
1
0
ZTCEN
REFLV
REFSL
TEMPE
BIASE
REFBE
Name
Type
Reset
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xD1; SFR Page = 0x00
Bit
7:6
5
Name
Unused Read = 00b; Write = don’t care.
ZTCEN Zero Temperature Coefficient Bias Enable Bit.
Function
0: ZeroTC Bias Generator automatically enabled when required.
1: ZeroTC Bias Generator forced on.
4
3
REFLV Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.20 V.
REFSL Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
2
1
0
TEMPE Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
REFBE On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin.
74
Rev. 1.1
SILICON [ SILICON ]
