C8051F50x-F51x
CAN Bit Time (4 to 25 tq)
Sync_Seg
Prop_Seg
Phase_Seg1
1 to 8 tq
Phase_Seg2
1 to 8 tq
1tq
1 to 8 tq
1tq
Sample Point
Figure 22.3. Four segments of a CAN Bit
The length of the 4 bit segments must be adjusted so that their sum is as close as possible to the desired
bit time. Since each segment must be an integer multiple of the time quantum (tq), the closest achievable
bit time is 24 tq (1000.008 ns), yielding a bit rate of 0.999992 Mbit/sec. The Sync_Seg is a constant 1 tq.
The Prop_Seg must be greater than or equal to the propagation delay of 400 ns and so the choice is 10 tq
(416.67 ns).
The remaining time quanta (13 tq) in the bit time are divided between Phase_Seg1 and Phase_Seg2 as
shown in. Based on this equation, Phase_Seg1 = 6 tq and Phase_Seg2 = 7 tq.
Phase_Seg1 + Phase_Seg2 = Bit_Time – (Synch_Seg + Prop_Seg)
1. If Phase_Seg1 + Phase_Seg2 is even, then Phase_Seg2 = Phase_Seg1. If the sum is odd,
Phase_Seg2 = Phase_Seg1 + 1.
2. Phase_Seg2 should be at least 2 tq.
Equation 22.1. Assigning the Phase Segments
The Synchronization Jump Width (SJW) timing parameter is defined by. It is used for determining the value
written to the Bit Timing Register and for determining the required oscillator tolerance. Since we are using
a quartz crystal as the system clock source, an oscillator tolerance calculation is not needed.
SJW = minimum (4, Phase_Seg1)
Equation 22.2. Synchronization Jump Width (SJW)
The value written to the Bit Timing Register can be calculated using Equation 18.3. The BRP Extension
register is left at its reset value of 0x0000.
BRPE = BRP – 1 = BRP Extension Register = 0x0000
SJWp = SJW – 1 = minimum (4, 6) – 1 = 3
TSEG1 = Prop_Seg + Phase_Seg1 - 1 = 10 + 6 – 1 = 15
TSEG2 = Phase_Seg2 – 1 = 6
Bit Timing Register = (TSEG2 x 0x1000) + (TSEG1 x 0x0100)
Bit Timing Register = (TSEG2 x 0x1000) + (TSEG1 x 0x0100) + (SJWp x 0x0040) + BRPE = 0x6FC0
Equation 22.3. Calculating the Bit Timing Register Value
Rev. 1.1
221
SILICON [ SILICON ]
