C8051F50x-F51x
22.1. Bosch CAN Controller Operation
The CAN Controller featured in the C8051F500/2/4/6/8-F510 devices is a full implementation of Bosch’s
full CAN module and fully complies with CAN specification 2.0B. A block diagram of the CAN controller is
shown in Figure 22.2. The CAN Core provides shifting (CANTX and CANRX), serial/parallel conversion of
messages, and other protocol related tasks such as transmission of data and acceptance filtering. The
message RAM stores 32 message objects which can be received or transmitted on a CAN network. The
CAN registers and message handler provide an interface for data transfer and notification between the
CAN controller and the CIP-51.
The function and use of the CAN Controller is detailed in the Bosch CAN User’s Guide. The User’s Guide
should be used as a reference to configure and use the CAN controller. This data sheet describes how to
access the CAN controller.
All of the CAN controller registers are located on SFR Page 0x0C. Before accessing any of the CAN regis-
ters, the SFRPAGE register must be set to 0x0C.
The CAN Controller is typically initialized using the following steps:
1. Set the SFRPAGE register to the CAN registers page (page 0x0C).
2. Set the INIT and the CCE bits to 1 in CAN0CN. See the CAN User’s Guide for bit definitions.
3. Set timing parameters in the Bit Timing Register and the BRP Extension Register.
4. Initialize each message object or set its MsgVal bit to NOT VALID.
5. Reset the INIT bit to 0.
CAN Controller
8051 MCU Core
RX
TX
CAN0CFG
Message
Handler
System Clock
CAN Core
Message
RAM
(32 Objects)
CAN Registers
mapped to
SFR space
Figure 22.2. CAN Controller Diagram
22.1.1. CAN Controller Timing
The CAN controller’s clock (fsys) is derived from the CIP-51 system clock (SYSCLK). The C8051F500/2/4/
6/8-F510 internal oscillator is accurate to within 0.5% and so an external oscillator is not required for CAN
communication. Refer to Section “4.10.4 Oscillator Tolerance Range” in the Bosch CAN User’s Guide for
further information regarding this topic.
The CAN controller clock must be less than or equal to 25 MHz. If the CIP-51 system clock is above
25 MHz, the divider in the CAN0CFG register must be set to divide the CAN controller clock down to an
appropriate speed.
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SILICON [ SILICON ]
