C8051F50x-F51x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F50x-F51x
Name
Pin
Pin
Pin
Type
Description
‘F500/1/4/5 F508/9- ‘F502/3/6/7
F510/1
(40-pin)
(48-pin)
(32-pin)
VDD
4
6
4
6
4
6
Digital Supply Voltage. Must be connected.
Digital Ground. Must be connected.
Analog Supply Voltage. Must be connected.
Analog Ground. Must be connected.
Voltage Regulator Input
GND
VDDA
GNDA
VREGIN
VIO
5
5
5
7
7
7
3
3
3
2
2
2
Port I/O Supply Voltage. Must be connected.
RST/
12
10
10
D I/O
Device Reset. Open-drain output of internal
POR or V Monitor. An external source
DD
can initiate a system reset by driving this pin
low.
Clock signal for the C2 Debug Interface.
C2CK
C2D
D I/O
D I/O
11
—
—
9
—
—
Bi-directional data signal for the C2 Debug
Interface.
P4.0/
D I/O or A In Port 4.0. See SFR Definition 20.29 for a
description.
Bi-directional data signal for the C2 Debug
Interface.
C2D
D I/O
P3.0/
—
8
9
8
D I/O or A In Port 3.0. See SFR Definition 20.24 for a
description.
Bi-directional data signal for the C2 Debug
Interface.
C2D
P0.0
D I/O
8
D I/O or A In Port 0.0. See SFR Definition 20.12 for a
description.
P0.1
P0.2
P0.3
P0.4
P0.5
1
1
1
D I/O or A In Port 0.1
D I/O or A In Port 0.2
D I/O or A In Port 0.3
D I/O or A In Port 0.4
D I/O or A In Port 0.5
48
47
46
45
40
39
38
37
32
31
30
29
22
Rev. 1.1
SILICON [ SILICON ]
