C8051F50x-F51x
VIO
Port I/O Configuration
Power On
Reset
CIP-51 8051
Controller Core
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/
P0.7
Digital Peripherals
Reset
up to 64 kB Byte Flash
Program Memory
UART0
Port 0
Drivers
Debug /
Programming
Hardware
C2CK/RST
Timers 0,
1, 2, 3
256 Byte RAM
4 kB XRAM
6 channel
Priority
C2D
PCA/WDT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Crossbar
Decoder
LIN 2.1
Voltage Regulator
(LDO)
Port 1
Drivers
CAN 2.0B
SPI
VREGIN
VDD
GND
I2C
Crossbar Control
SFR
Bus
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
External Memory Interface
*On ‘F508-F510 devices
System Clock Setup
XTAL1 XTAL2
Port 2
Drivers
Analog Peripherals
Internal Oscillator
External Oscillator
Voltage
Reference
Clock Multiplier
VREF
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
VDD
VREF
Port 3
Drivers
VDD
VREF
P0 – P3
A
M
U
X
12-bit
200ksps
ADC
Temp
Sensor
P4.0 / C2D
GND
Port 4
Driver
CP0, CP0A
+
-
VDDA
GNDA
Comparator 0
CP1, CP1A
+
-
Comparator 1
Figure 1.2. C8051F508/9-F510/1 Block Diagram
18
Rev. 1.1
SILICON [ SILICON ]
