C8051F50x-F51x
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0
Bit
7
6
5
4
3
2
1
0
CP1AE
CP1E
CP0AE
CP0E
SMB0E
SPI0E
CAN0E
URT0E
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xE1; SFR Page = 0x0F
Bit
Name
Function
7
CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
6
5
4
3
2
CP1E
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
1
0
CAN0E CAN I/O Output Enable.
0: CAN I/O unavailable at Port pins.
1: CAN_TX, CAN_RX routed to Port pins P0.6 and P0.7.
URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
184
Rev. 1.1
SILICON [ SILICON ]
