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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition  
20.13 for the PnMDIN register details.  
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-  
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is  
required even for the digital resources selected in the XBRn registers, and is not automatic. The only  
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the  
PnMDOUT settings. When the WEAKPUD bit in XBR2 is 0, a weak pullup is enabled for all Port I/O config-  
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is  
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.  
Registers XBR0, XBR1, and XBR2 must be loaded with the appropriate values to select the digital I/O  
functions required by the design. Setting the XBARE bit in XBR2 to 1 enables the Crossbar. Until the  
Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn  
Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority  
Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter-  
mine the Port I/O pin-assignments based on the XBRn Register settings.  
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers  
are disabled while the Crossbar is disabled.  
Rev. 1.1  
183