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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
SFR Page  
Stack SFR's  
0x0  
(SPI0DAT)  
SFRPAGE  
SFRNEXT  
SFRLAST  
Figure 13.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT  
While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt  
occurs. The CIP-51 vectors to the CAN0 ISR and pushes the current SFR Page value (SFR Page 0x00)  
into SFRNEXT in the SFR Page Stack. The SFR page needed to access CAN’s SFRs is then automatically  
placed in the SFRPAGE register (SFR Page 0x0C). SFRPAGE is considered the “top” of the SFR Page  
Stack. Software can now access the CAN0 SFRs. Software may switch to any SFR Page by writing a new  
value to the SFRPAGE register at any time during the CAN0 ISR to access SFRs that are not on SFR  
Page 0x0C. See Figure 13.3.  
102  
Rev. 1.1  
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