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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
12. CIP-51 Microcontroller  
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the  
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-  
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51  
also includes on-chip debug hardware (see description in Section 26), and interfaces directly with the ana-  
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-  
grated circuit.  
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as  
additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram).  
The CIP-51 includes the following features:  
- Fully Compatible with MCS-51 Instruction  
Set  
- Extended Interrupt Handler  
- Reset Input  
- 25 MIPS Peak Throughput with 25 MHz  
Clock  
- Power Management Modes  
- On-chip Debug Logic  
- 0 to 25 MHz Clock Frequency  
- Program and Data Memory Security  
Performance  
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-  
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system  
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51  
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more  
than eight system clock cycles.  
DATA BUS  
ACCUMULATOR  
B
REGISTER  
STACK POINTER  
TMP1  
TMP2  
SRAM  
ADDRESS  
REGISTER  
PSW  
SRAM  
ALU  
DATA BUS  
SFR_ADDRESS  
SFR_CONTROL  
BUFFER  
D8  
SFR  
BUS  
INTERFACE  
D8  
SFR_WRITE_DATA  
SFR_READ_DATA  
D8  
DATA POINTER  
PC INCREMENTER  
D8  
MEM_ADDRESS  
MEM_CONTROL  
PROGRAM COUNTER (PC)  
PRGM. ADDRESS REG.  
PIPELINE  
MEMORY  
INTERFACE  
A16  
D8  
MEM_WRITE_DATA  
MEM_READ_DATA  
CONTROL  
LOGIC  
RESET  
CLOCK  
SYSTEM_IRQs  
INTERRUPT  
INTERFACE  
EMULATION_IRQ  
D8  
STOP  
IDLE  
POWER CONTROL  
REGISTER  
D8  
Figure 12.1. CIP-51 Block Diagram  
72  
Rev. 0.2