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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
25.3.3. High-Speed Output Mode  
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs  
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and  
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An  
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-  
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared  
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-  
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next  
match event.  
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-  
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the  
ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.  
Write to  
0
PCA0CPLn  
ENB  
Reset  
PCA0CPMn  
Write to  
PCA0CPHn  
P E C C M T P E  
W C A A A O W C  
M O P P T G M C  
1 M P N n n n F  
ENB  
1
6 n n n  
n
n
x
0 0  
0
x
PCA Interrupt  
PCA0CN  
C C C C C  
F R  
C C C  
F F F  
2 1 0  
PCA0CPLn  
PCA0CPHn  
0
1
Enable  
Match  
16-bit Comparator  
TOGn  
Toggle  
0
CEXn  
Crossbar  
Port I/O  
1
PCA  
Timebase  
PCA0L  
PCA0H  
Figure 25.6. PCA High-Speed Output Mode Diagram  
Rev. 0.2  
215