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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)  
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The  
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,  
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0  
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled  
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls  
the Timer 1 interrupt.  
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,  
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,  
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC  
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-  
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,  
configure it for Mode 3.  
CKCON  
TMOD  
G C T T G C T T  
T T T T T T S S  
3 3 2 2 1 0 C C  
M M M M M M A A  
A
/ 1 1 A / 0 0  
T T M M T T M M  
E 1 1 0 E 0 1 0  
H L H L  
1 0  
1
0
Pre-scaled Clock  
SYSCLK  
0
1
TH0  
(8 bits)  
TR1  
TF1  
TR1  
TF0  
TR0  
IE1  
Interrupt  
Interrupt  
0
1
IT1  
IE0  
IT0  
T0  
TL0  
(8 bits)  
TR0  
Crossbar  
GATE0  
IN0PL  
XOR  
/INT0  
Figure 24.3. T0 Mode 3 Block Diagram  
192  
Rev. 0.2