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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload  
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start  
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all  
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If  
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is  
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be  
correct. When in Mode 2, Timer 1 operates identically to Timer 0.  
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the  
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0  
is active as defined by bit IN0PL in register IT01CF (see Section “15.3. External Interrupts /INT0 and  
/INT1” on page 96 for details on the external input signals /INT0 and /INT1).  
CKCON  
TMOD  
IT01CF  
G C T T G C T T  
I I I I I I I I  
N N N N N N N N  
T T T T T T S S  
3 3 2 2 1 0 C C  
M M M M M M A A  
A
/
1
1 A  
/
0
0
T T M M T T M M  
1
1 1 1 0 0 0 0  
E 1  
1
1
0 E 0  
0
1
0
P S S S P S S S  
H L H L  
1 0  
L
L
2
L
1
L
0
L
L
2
L
1
L
0
Pre-scaled Clock  
SYSCLK  
0
1
0
1
T0  
TF1  
TR1  
TF0  
TR0  
IE1  
TCLK  
TL0  
(8 bits)  
Interrupt  
TR0  
IT1  
IE0  
IT0  
Crossbar  
GATE0  
TH0  
Reload  
(8 bits)  
IN0PL  
XOR  
/INT0  
Figure 24.2. T0 Mode 2 Block Diagram  
Rev. 0.2  
191