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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode  
Bit  
7
6
ECOMn  
R/W  
0
5
CAPPn  
R/W  
0
4
CAPNn  
R/W  
0
3
MATn  
R/W  
0
2
TOGn  
R/W  
0
1
PWMn  
R/W  
0
0
ECCFn  
R/W  
0
Name PWM16n  
Type  
R/W  
0
Reset  
SFR Addresses: PCA0CPM0 = 0xDA, PCA0CPM1 = 0xDB, PCA0CPM2 = 0xDC  
Bit  
Name  
Function  
7
PWM16n 16-bit Pulse Width Modulation Enable.  
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.  
0: 8 to 11-bit PWM selected.  
1: 16-bit PWM selected.  
6
5
4
3
ECOMn Comparator Function Enable.  
This bit enables the comparator function for PCA module n when set to ‘1’.  
CAPPn Capture Positive Function Enable.  
This bit enables the positive edge capture for PCA module n when set to ‘1’.  
CAPNn Capture Negative Function Enable.  
This bit enables the negative edge capture for PCA module n when set to ‘1’.  
MATn  
Match Function Enable.  
This bit enables the match function for PCA module n when set to ‘1’. When enabled,  
matches of the PCA counter with a module's capture/compare register cause the CCFn  
bit in PCA0MD register to be set to logic 1.  
2
1
0
TOGn  
Toggle Function Enable.  
This bit enables the toggle function for PCA module n when set to ‘1’. When enabled,  
matches of the PCA counter with a module's capture/compare register cause the logic  
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-  
ates in Frequency Output Mode.  
PWMn Pulse Width Modulation Mode Enable.  
This bit enables the PWM function for PCA module n when set to ‘1’. When enabled, a  
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if  
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is  
also set, the module operates in Frequency Output Mode.  
ECCFn Capture/Compare Flag Interrupt Enable.  
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.  
0: Disable CCFn interrupts.  
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.  
Note: When the WDTE bit is set to ‘1’, the PCA0CPM2 register cannot be modified, and module 2 acts as the  
watchdog timer. To change the contents of the PCA0CPM2 register or the function of module 2, the Watchdog  
Timer must be disabled.  
226  
Rev. 0.2  
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