C8051F336/7/8/9
SFR Definition 25.2. PCA0MD: PCA Mode
Bit
7
CIDL
R/W
0
6
WDTE
R/W
1
5
WDLCK
R/W
0
4
3
CPS2
R/W
0
2
CPS1
R/W
0
1
CPS0
R/W
0
0
Name
Type
Reset
ECF
R/W
0
R
0
SFR Address = 0xD9
Bit
Name
Function
7
CIDL
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6
5
WDTE Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
WDLCK Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
UNUSED Unused. Read = 0b, Write = Don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
0
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to ‘1’, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
224
Rev. 0.2
SILICON [ SILICON ]
