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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Reset  
SCR[7:0]  
R/W  
0
0
0
0
0
0
0
0
SFR Address = 0xA2  
Bit  
Name  
Function  
7:0  
SCR[7:0]  
SPI0 Clock Rate.  
These bits determine the frequency of the SCK output when the SPI0 module is  
configured for master mode operation. The SCK clock frequency is a divided ver-  
sion of the system clock, and is given in the following equation, where SYSCLK is  
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR  
register.  
SYSCLK  
2 × (SPI0CKR[7:0] + 1)  
----------------------------------------------------------  
=
fSCK  
for 0 <= SPI0CKR <= 255  
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,  
2000000  
-------------------------  
=
fSCK  
2 × (4 + 1)  
fSCK = 200kHz  
SFR Definition 23.4. SPI0DAT: SPI0 Data  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Reset  
SPI0DAT[7:0]  
R/W  
0
0
0
0
0
0
0
0
SFR Address = 0xA3  
Bit Name  
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.  
Function  
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to  
SPI0DAT places the data into the transmit buffer and initiates a transfer when in  
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.  
Rev. 0.2  
183