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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
SCK  
(CKPOL=0, CKPHA=0)  
SCK  
(CKPOL=1, CKPHA=0)  
MOSI  
MSB  
MSB  
Bit 6  
Bit 6  
Bit 5  
Bit 5  
Bit 4  
Bit 4  
Bit 3  
Bit 3  
Bit 2  
Bit 2  
Bit 1  
Bit 1  
Bit 0  
Bit 0  
MISO  
NSS (4-Wire Mode)  
Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0)  
SCK  
(CKPOL=0, CKPHA=1)  
SCK  
(CKPOL=1, CKPHA=1)  
MOSI  
MSB  
MSB  
Bit 6  
Bit 6  
Bit 5  
Bit 5  
Bit 4  
Bit 4  
Bit 3  
Bit 3  
Bit 2  
Bit 2  
Bit 1  
Bit 1  
Bit 0  
Bit 0  
MISO  
NSS (4-Wire Mode)  
Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1)  
23.6. SPI Special Function Registers  
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN  
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate  
Register. The four special function registers related to the operation of the SPI0 Bus are described in the  
following figures.  
180  
Rev. 0.2