C8051F336/7/8/9
SFR Definition 18.1. VDM0CN: V Monitor Control
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Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT
Type
R/W
R
R
0
R
0
R
0
R
0
R
0
R
0
Reset
Varies
Varies
SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
V
Monitor Enable.
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This bit turns the V monitor circuit on/off. The V Monitor cannot generate sys-
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DD
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 18.2). Selecting the V monitor as a reset source before it has stabilized
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may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V Monitor and selecting it as a
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reset source. See Table 6.4 for the minimum V Monitor turn-on time.
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0: V Monitor Disabled.
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1: V Monitor Enabled.
DD
6
VDDSTAT
UNUSED
V
Status.
DD
This bit indicates the current power supply status (V Monitor output).
0: V is at or below the V monitor threshold.
1: V is above the V monitor threshold.
DD
DD
DD
DD
DD
5:0
Unused. Read = 000000b; Write = Don’t care.
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 6.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
Rev. 0.2
113
SILICON [ SILICON ]
