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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
18.1. Power-On Reset  
During power-up, the device is held in a reset state and the RST pin is driven low until V settles above  
DD  
V
. A delay occurs before the device is released from reset; the delay decreases as the V ramp time  
RST  
DD  
increases (V  
ramp time is defined as how fast V  
ramps from 0 V to V ). Figure 18.2. plots the  
RST  
DD  
DD  
power-on and V  
monitor reset timing. The maximum V  
ramp time is 1 ms; slower ramp times may  
DD  
DD  
cause the device to be released from reset before V reaches the V  
level. For ramp times less than  
DD  
RST  
1 ms, the power-on reset delay (T  
) is typically less than 0.3 ms.  
PORDelay  
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is  
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other  
resets). Since all resets cause program execution to begin at the same location (0x0000) software can  
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-  
ory should be assumed to be undefined after a power-on reset. The V  
power-on reset.  
monitor is enabled following a  
DD  
VDD  
2.70  
2.55  
VRST  
2.0  
1.0  
t
/RST  
Logic HIGH  
TPORDelay  
Logic LOW  
VDD  
Power-On  
Reset  
Monitor  
Reset  
Figure 18.2. Power-On and V Monitor Reset Timing  
DD  
Rev. 0.2  
111