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18.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V settles above
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V
. A delay occurs before the device is released from reset; the delay decreases as the V ramp time
RST
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increases (V
ramp time is defined as how fast V
ramps from 0 V to V ). Figure 18.2. plots the
RST
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power-on and V
monitor reset timing. The maximum V
ramp time is 1 ms; slower ramp times may
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cause the device to be released from reset before V reaches the V
level. For ramp times less than
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RST
1 ms, the power-on reset delay (T
) is typically less than 0.3 ms.
PORDelay
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
monitor is enabled following a
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VDD
2.70
2.55
VRST
2.0
1.0
t
/RST
Logic HIGH
TPORDelay
Logic LOW
VDD
Power-On
Reset
Monitor
Reset
Figure 18.2. Power-On and V Monitor Reset Timing
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Rev. 0.2
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SILICON [ SILICON ]
