C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 9.1. SFR0CN: SFR Page Control
SFR Page:
F
SFR Address: 0xE5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved Reserved SFRPGEN 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–1: RESERVED. Read = 0000000b. Must Write 0000000b.
Bit 0:
SFRPGEN: SFR Automatic Page Control Enable.
Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and auto-
matically switch to SFR page 0. This bit is used to control this autopaging function.
0: SFR Automatic Paging disabled. C8051 core will not automatically change to SFR page
0.
1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will automatically switch to
SFR page 0.
SFR Definition 9.2. SFRPAGE: SFR Page
SFR Page:
all pages
SFR Address: 0xA7
R/W
R/W
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
Bit7
Bit6
Bits 7–0: SFR Page Bits: Byte Represents the SFR Page the C8051 MCU uses when reading or mod-
ifying SFR’s.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 MCU is using.
When enabled in the SFR Page Control Register (SFR0CN), the C8051 will automatically
switch to SFR Page 0x00 and return to the previous SFR page upon return from interrupt
(unless SFR Stack was altered before a returning from the interrupt).
SFRPAGE is the top byte of the SFR Page Stack, and push/pop events of this stack are
caused by interrupts (and not by reading/writing to the SFRPAGE register)
94
Rev. 1.0
SILICON [ SILICON ]
