C8051F360/1/2/3/4/5/6/7/8/9
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F36x
Pin
Pin
Pin
Name ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 Type
Description
(48-pin) (32-pin)
(28-pin)
V
19, 31, 43
4
4
Power Supply Voltage.
DD
GND 18, 30, 42
3
3
Ground.
—
—
—
—
AGND
AV+
6
7
Analog Ground.
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
RST/
8
5
5
D I/O Device Reset. Open-drain output of internal POR or
V
Monitor. An external source can initiate a system
DD
reset by driving this pin low for at least 10 µs.
C2CK
P4.6/
D I/O Clock signal for the C2 Debug Interface.
—
6
—
6
9
D I/O or Port 4.6. See Section 17 for a complete description.
A In
C2D
D I/O Bi-directional data signal for the C2 Debug Interface.
—
P3.0/
D I/O or Port 3.0. See Section 17 for a complete description.
A In
C2D
P0.0
D I/O Bi-directional data signal for the C2 Debug Interface.
5
4
2
2
D I/O or Port 0.0. See Section 17 for a complete description.
A In
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
1
1
D I/O or Port 0.1. See Section 17 for a complete description.
A In
3
32
31
30
29
28
27
28
27
26
25
24
23
D I/O or Port 0.2. See Section 17 for a complete description.
A In
2
D I/O or Port 0.3. See Section 17 for a complete description.
A In
1
D I/O or Port 0.4. See Section 17 for a complete description.
A In
48
47
46
D I/O or Port 0.5. See Section 17 for a complete description.
A In
D I/O or Port 0.6. See Section 17 for a complete description.
A In
D I/O or Port 0.7. See Section 17 for a complete description.
A In
36
Rev. 1.0
SILICON [ SILICON ]
