C8051F360/1/2/3/4/5/6/7/8/9
Table 20.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing* (See Figure 20.8 and Figure 20.9)
T
T
T
T
SCK High Time
1 x T
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
SCK Low Time
1 x T
1 x T
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
+ 20
SYSCLK
0
MIH
Slave Mode Timing* (See Figure 20.10 and Figure 20.11)
T
T
T
T
T
T
T
T
T
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
2 x T
2 x T
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SE
SYSCLK
SD
SYSCLK
—
4 x T
SYSCLK
SEZ
SDZ
CKH
CKL
SIS
—
4 x T
SYSCLK
5 x T
5 x T
2 x T
2 x T
—
SYSCLK
SYSCLK
SYSCLK
SCK Low Time
—
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
SIH
SOH
SYSCLK
—
4 x T
8 x T
SYSCLK
SYSCLK
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x T
SYSCLK
T
SLH
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
246
Rev. 1.0
SILICON [ SILICON ]
