C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 15.2. EMI0CF: External Memory Configuration
SFR Page:
F
SFR Address: 0xC7
R/W
R/W
–
R/W
–
R/W
EMD2
Bit4
R/W
EMD1
Bit3
R/W
EMD0
Bit2
R/W
EALE1
Bit1
R/W
Reset Value
–
Bit7
EALE0 00000011
Bit0
Bit6
Bit5
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bit 4: EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
Bits 3–2: EMD1–0: EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space.
01: Split Mode without Bank Select: Accesses below the 1 k boundary are directed on-chip.
Accesses above the 1 k boundary are directed off-chip. 8-bit off-chip MOVX operations
use the current contents of the Address High port latches to resolve upper address byte.
Note that in order to access off-chip space, EMI0CN must be set to a page that is not
contained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 1 k boundary are directed on-chip.
Accesses above the 1 k boundary are directed off-chip. 8-bit off-chip MOVX operations
use the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the
CPU.
Bits 1–0: EALE1–0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
156
Rev. 1.0
SILICON [ SILICON ]
