C8051F360/1/2/3/4/5/6/7/8/9
13.3. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V , system clock frequency, or temperature. This accidental execution of Flash modi-
DD
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the V
Monitor must be enabled and
DD
enabled as a reset source on C8051F36x devices for the Flash to be successfully modified. If either the
Monitor or the V Monitor reset source is not enabled, a Flash Error Device Reset will be gen-
V
DD
DD
erated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.3.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the minimum V rise time specification of 1 ms is met. If the system cannot
DD
meet this rise time specification, then add an external V brownout circuit to the /RST pin of
DD
the device that holds the device in reset until V
reaches V
and re-asserts /RST if V
RST DD
DD
drops below V
. Please see Table 12.1, “Reset Electrical Characteristics,” on page 134 for
RST
more information on the VDD Monitor Threshold voltage (V
).
RST
3. Keep the on-chip V Monitor enabled and enable the V Monitor as a reset source as early
DD
DD
in code as possible. This should be the first set of instructions executed after the Reset Vector.
For 'C'-based systems, this will involve modifying the startup code added by the 'C' compiler.
See your compiler documentation for more details. Make certain that there are no delays in
software between enabling the V Monitor and enabling the V Monitor as a reset source.
DD
DD
Code examples showing this can be found in AN201, "Writing to Flash from Firmware", avail-
able from the Silicon Laboratories web site.
Note: On C8051F36x devices, both the V Monitor and the V Monitor reset source must
DD
DD
be enabled to write or erase Flash without generating a Flash Error Device Reset.
4. As an added precaution, explicitly enable the V Monitor and enable the V Monitor as a
DD
DD
reset source inside the functions that write and erase Flash memory. The V Monitor enable
DD
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
140
Rev. 1.0
SILICON [ SILICON ]
