C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 10.5. EIE2: Extended Interrupt Enable 2
SFR Page:
all pages
SFR Address: 0xE7
R/W
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
EMAT
Bit1
R/W
–
Reset Value
–
Bit7
00000000
Bit6
Bit5
Bit4
Bit3
Bit2
Bit0
Bits 7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit 1:
EMAT: Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable the Port Match interrupt.
1: Enable the Port Match interrupt.
Bit 0:
UNUSED. Read = 0b. Write = don’t care.
SFR Definition 10.6. EIP2: Extended Interrupt Priority 2
SFR Page:
F
SFR Address: 0xCF
R/W
R/W
R/W
–
R/W
–
R/W
–
R/W
–
R/W
PMAT
Bit1
R/W
–
Reset Value
–
Bit7
–
Bit6
00000000
Bit5
Bit4
Bit3
Bit2
Bit0
Bits 7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit 1:
PMAT: Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
UNUSED. Read = 0b. Write = don’t care.
Bit 0:
114
Rev. 1.0
SILICON [ SILICON ]
