Si510/511
3. Pin Descriptions
VDD
1
2
4
OE
VDD
VDD
1
2
3
6
5
4
1
2
3
6
5
4
OE
NC
NC
OE
CLK–*
CLK+
CLK–*
CLK+
GND
3
CLK
GND
GND
Si510 (CMOS)
Si510 (LVDS/LVPECL/HCSL/Dual CMOS*)
Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)
*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”.
Table 11. Si510 Pin Descriptions (CMOS)
Pin
Name
CMOS Function
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
Electrical and Case Ground.
1
OE
2
3
4
GND
CLK
Clock Output.
Power Supply Voltage.
V
DD
Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)
Pin
Name
NC
LVPECL/LVDS/HCSL Function
No connect. Make no external connection to this pin.
1
2
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
Electrical and Case Ground.
OE
3
4
5
6
GND
CLK+
CLK–
Clock Output.
Complementary Clock Output.
Power Supply Voltage.
V
DD
Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)
Pin
Name
LVPECL/LVDS/HCSL Function
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
No connect. Make no external connection to this pin.
1
OE
2
3
4
5
6
NC
Electrical and Case Ground.
Clock Output.
GND
CLK+
CLK–
Complementary Clock Output.
Power Supply Voltage.
V
DD
12
Rev. 1.4
SILICON [ SILICON ]
