CMOS SERIAL E2PROM
S-93C46A/56A/66A
n
Receiving a Start-Bit
Both the recognition of a start-bit and the VERIFY procedure occur when CS is “high”. Therefore, only after a write
operation, in order to accept the next command by having CS go high, the DO pin switch from a state of high-impedence to
a state of data output; but if it recognizes a start-bit, the DO pin returns to a state of high-impedence.
n
Three-wire Interface (DI-DO direct connection)
Although the normal configuration of a serial interface is a 4-wire interface to CS, SK, DI, and DO, a 3-wire interface is
also a possibility by connecting DI and DO. However, since there is a possibility that the DO output from the serial memory
IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between DI and DO in order to
give preference to data output from the CPU to DI(See Figure 22).
CPU
S-93C46A/56A/66A
SIO
DI
DO
R : 10k ~ 100kW
Figure 22
Seiko Instruments Inc.
13
SII [ SEIKO INSTRUMENTS INC ]
