CMOS SERIAL E2PROM
S-93C46A/56A/66A
2.3 WRAL
This instruction writes the same 16-bit data into every address.
After changing CS to high, input a start-bit, op-code (WRAL), address (optional), and 16-bit data. If there is a data overflow
of more than 16 bits, only the last 16 bits of the data is considered valid. Changing CS to low will start the WRAL operation.
It is not necessary to make the data "1" before initiating the WRAL operation.
tCDS
CS
VERIFY
SK
DI
1
2
0
3
4
5
6
7
8
9
10
25
D0
0
0
D15
1
1
4Xs
tSV
tHZ1
Hi-Z
busy
ready
DO
Hi-Z
tPR
Figure 13 WRAL Timing (S-93C46A)
tCDS
CS
SK
VERIFY
1
2
3
4
5
6
7
8
9
10 11 12
D15
27
0
0
0
D0
DI
1
1
tSV
tHZ1
6Xs
Hi-Z
busy
ready
DO
Hi-Z
tPR
Figure 14 WRAL Timing (S-93C56A)
tCDS
CS
SK
VERIFY
1
2
0
3
4
5
6
7
8
9
10 11 12
D15
27
DI
0
0
D0
1
1
tSV
tHZ1
6Xs
Hi-Z
busy
ready
DO
Hi-Z
tPR
Figure 15 WRAL Timing (S-93C66A)
Seiko Instruments Inc.
10
SII [ SEIKO INSTRUMENTS INC ]
