HIGH WITHSTAND-VOLTAGE VOLTAGE REGULATOR WITH RESET FUNCTION
S-87x Series
Rev.7.2_00
4. Delay circuit
The delay circuit outputs voltage detector output (VOR) with delay after the voltage at VIN pin has become
release voltage (+VDET) at the rising of VIN pin.
In Figure 22, when Vcd exceeds the reference voltage (Vref), the output voltage pin detection voltage
output (VOR) changes from low to high level, providing delay output. When the voltage at VIN pin falls
under the detection voltage (−VDET), the N2 transistor turns ON, therefore the charge of the external
capacitor (CD) is rapidly discharged and the voltage detector output (VOR) changes from high to low level
without delay.
The external capacitor (CD) is charged with constant current, and is practically independent of VIN voltage.
Its delay time (tpd) is expressed by the following equation:
tpd (ms)=Delay coefficient (3.18 min., 5.74 typ., 8.73 max.)×CD (nF)
IC
Vcd
+
−
N2
VOR
Vref
CD
CD
Figure 22
Caution 1. Unless an output delay is needed, keep CD pin open. Do not apply external voltage
other than ground potential to CD pin, which may cause IC breakdown.
2. When designing your printed-circuit board layout, take care that no leakage current
flows to the external capacitor (CD), otherwise the correct delay time may not be
obtained. Because the value of the constant current source (IC) is only 195 nA, CD to
impedance is high.
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Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
