LOW DROPOUT CMOS VOLTAGE REGULATOR
S-818 Series
Rev.1.2
Selection of Output Capacitor (CL)
The S-818 series needs an output capacitor between VOUT pin and VSS pin for phase compensation. A small
ceramic or an OS electrolytic capacitor of 2 µF or more can be used. If a tantalum or an aluminum electrolytic
capacitor is used, its capacitance must be 2 µF or more and the ESR must be 10 Ω or less.
Attention should be paid not to cause an oscillation due to increase of ESR at low temperatures when using an
aluminum electrolytic capacitor.
Evaluate the performance including temperature characteristics before prototyping the circuit.
Overshoot and undershoot characteristics differ depending upon the type of the output capacitor. Refer to output
capacitor dependence data in transient response characteristics .
Design Considerations
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Design wiring patterns for VIN, VOUT and GND pins to decrease impedance.
When mounting an output capacitor, connection from the capacitor to the VOUT pin and to the VSS pin
should be as close as possible.
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Note that output voltage may increase when the voltage regulator is used at low load current (less than 10
µA).
To prevent oscillation, it is recommended to use the external components under the following conditions:
* Input capacitor (CIN): 0.47 µF or more
* Output capacitor (CL): 2 µF or more
* Equivalent Series Resistance (ESR): 10 Ω or less
* Input series resistance (RIN): 10 Ω or less
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The voltage regulator may oscillate when the impedance of the power supply is high and the input
capacitor is small or not connected.
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Be sure that input voltage and load current do not exceed the power dissipation level of the package.
SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
In determining necessary output current, consider the value of output current of Table 4 “Electrical
Characteristics” and Note *5) (page 4).
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Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
