2-WIRE CMOS SERIAL E2PROM
S-24CS01A/02A/04A/08A
Rev.4.4_00
6. Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of the E2PROM are changed at the same time, it is necessary to prevent the start/stop
condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly
recognized during communication, the E2PROM enters the standby status.
It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µs minimum in the S-
24CS01A/02A/04A/08A. This is to prevent time lag caused by the load of the bus line from generating the
stop (or start) condition.
tHD.DAT = 0.3 µs Min.
SCL
SDA
Figure 30 E2PROM Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-24CS01A/02A/04A/08A includes a built-in low-pass filter to suppress noise at the SDA and SCL
pins. This means that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can
be suppressed.
The guaranteed for details, refer to noise suppression time (tI) in Table 12.
300
200
100
Noise suppression time (tI) Max.
[ns]
2
3
4
5
Power supply voltage (VCC)
[V]
Figure 31 Noise Suppression Time for SDA and SCL Pins
26
Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
